Currently, in the power transistors with breakdown voltage over 1000V market is mostly occupied by silicon base insulated gate bipolar transistor (IGBT). However, owing to the bipolar carriers characteristic of IGBT devices, the devices will suffer problems of the lifetime of the minority while turning the device off. Consequently, if it could not to add lifetime killers in the manufacture process, the system should have to tolerate the power consumption and time waste while turning off IGBT devices.
By contrast, silicon base metal oxide semiconductor field transistor features with mono-carrier species, as a result, it provides faster switch speed and less extra power consumption than those bipolar IGBTs. This is because the silicon carbide having large energy band gap of about 3.26 eV, high critical breakdown electric field intensity and high conductivity (4.9 W/cm-k) and is envisioned as an excellent material for power transistor. The power transistor based on silicon carbide can come up to a benchmark of 1000V breakdown voltage without suffering any difficulty. The breakage voltage can even come up to 5 kV if the epi-layer thickness is appropriately adjusted.
Thus, it is prone to develop silicon carbide base power transistor replaced for silicon IGBT. According to the estimation in theory, under a condition of the same breakdown voltage, the power transistor formed of silicon carbide has a Ron, sp (sheet resistance for transistor operates at a liner region) of Id vs Vd only about 1/200 to 1/400 of conventional power transistor.
For the purpose of acquiring a normal-off device, most of the conventional silicon carbide MOSFETs are operated in an inversion channel type. An example is U.S. Pat. No. 5,506,421, issued to Palmour, with a title of “Power MOSFET in Silicon Carbide.” Please refer to FIG. 1A that illustrates a cross-sectional view of the silicon carbide MOSFET with an inversion channel. In this figure, a drain region consisting of a silicon carbide substrate 10 has n-type impurities in heavily doped and a drift layer 12 has lightly doped n-type impurities. A layer over the drift layer 12 is a p-type epi-layer 14. The p-type epi-layer 14 comprises trenches 27 formed therein and having trench bottoms thereof come down into the drift layer 12. An oxide layer formed on the bottoms and sidewalls of the trenches and extended to the upper surface of the p-type epi-layer 14. Poly gates with contacts 30 thereof are then formed on the gate oxide layer 31. Moreover, the source contacts 22 are formed over both he p-type epi-layer 14 and n+ doped regions 18 where the n+ doped regions 18 are formed on the two sides of each trench 27 so as to keep the source contacts 22 remain at the same voltage level. In the figure, the termination region 35 and oxide layer 36 formed thereover are shown. The deficiency of about the forgoing MOSFET is with a large RON,sp, the specific on-resistance in the linear operating region of the transistor while turning on.
To reduce the RON,sp, the MOSFET of accumulation channel type may provide a good solution. The accumulation channel make channel of the electron migration from inducing an inversion channel, where the channel is near the surface of the silicon carbide substrate turn into the interior bulk region of the silicon carbide substrate. Increasing the electron mobility and reduce the RON,sp, of the device are thus anticipated.
An example of accumulation channel type silicon carbide MOSFET is U.S. Pat. No. 6,281,521 with a title “Silicon Carbide Horizontal Channel Buffered Gate Semiconductor Devices” issued to Singh. The device structure of the patent proposed is shown in FIG. 1C, which is a planar device. The feature of the device is no gate oxide layer but a p-type gate layer 16 lie in between the gate contact layer 20 and the drift layer 12. The drift layer 12 is formed on the silicon carbide substrate 10. While exerting a bias voltage to the gate contact 20, an accumulation channel is formed on the upper portion of the drift layer 15. As the gate voltage is grounded, the channel presents pinch-off in between the p+ base region 14 and the gate layer. 16.
To make the transistor becoming a normally off (i.e. no gate bias voltage, no current flow occurs), the doping concentration in the drift layer 12, the p+ base region 14 and the gate layer 16 have to appropriately restricted, and so does the spacing in between the p+ base layer 14 and the gate layer 16. In the situation, the channel region 15 is completely depleted.
The proposed Singh's patent had reached the aim of decreasing Ron,sp. However, the area occupied for a planar MOSFET is larger than for a typical trench MOSFET.
The motivation of the present invention is thus to propose a trench MOSFET of accumulation channel type so as to increase the electron mobility and thus reduce the Ron,sp.